It utilizes Verilog models and testbenches to implement fault simulation and test generation algorithms.
The book by Zainalabedin Navabi (2010) is a comprehensive guide that bridges the gap between digital design and testing methodologies. Unlike traditional texts, it uses Verilog HDL to describe and simulate test hardware, making complex concepts like fault simulation and test generation more practical and less ambiguous for designers. Core Features and Methodology Digital System Test and Testable Design: Using ...
The text treats testing and testability as integral parts of the digital design process rather than afterthoughts. It utilizes Verilog models and testbenches to implement